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vishay siliconix dg408l, dg409l document number: 71342 s11-1066-rev. g, 30-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 precision 8-ch/dual 4-ch lo w voltage analog multiplexers description the dg408l, dg409l are low voltage pin-for-pin compatible companion devices to the indu stry standard dg408, dg409 with improved performance. using bicmos wafer fabrication technology allows the dg408l, dg409l to operate on single and dual supplies. single supply voltage ranges from 3 v to 12 v while dual supply operation is recommended with 3 v to 6 v. the dg408l is an 8 channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3 bit binary address (a 0 , a 1 , a 2 ). the dg409l is a dual 4 channel differential analog multiplexer designed to connect one of four differential inputs to a common dual output as determined by its 2 bit binary address (a 0 , a 1 ). break-before-make switching action to protect against momentary crosstalk between adjacent channels. the dg408l, dg409l provides lower on-resistance, faster switching time, lower leakage, less power consumption and higher off-isolation than the dg408, dg409. features ? halogen-free according to iec 61249-2-21 definition ? pin-for-pin compatibility with dg408, dg409 ? 2.7 v to 12 v single supply or 3 v to 6 v dual supply operation ? lower on-resistance: r ds(on) - 17 ? typ. ? fast switching: t on - 38 ns, t off - 18 ns ? break-before-make guaranteed ? low leakage: i s(off) - 0.2 na max. ? low charge injection: 1 pc ? ttl, cmos, lv logic (3 v) compatible ? 82 db off-isolation at 1 mhz ? 2000 v esd protection (hbm) ? compliant to rohs directive 2002/95/ec benefits ? high accuracy ? single and dual power rail capacity ? wide operating voltage range ? simple logic interface applications ? data acquisition systems ? battery operated equipment ? portable test equipment ? sample and hold circuits ? communication systems ?sdsl, dslam ? audio and video signal routing functional block diagrams and pin configurations * pb containing terminations are not rohs compliant, exemptions may apply a 0 d a a 1 d b en gnd v- v+ s 1a s 1b s 2a s 2b s 3a s 3b s 4a s 4b decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg409l dual-in- line, soic and tssop s 3 a 0 s 6 d s 4 a 1 s 8 s 7 en a 2 v- gnd s 1 v+ s 2 s 5 decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg408l dual-in- line, soic and tssop
www.vishay.com 2 document number: 71342 s11-1066-rev. g, 30-may-11 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 logic "0" = v al ? 0.8 v logic "1" = v ah ? 2.4 v x = do not care for low and high voltage levels for v ax and v en consult ?digital control? param eters for specific v+ operation. notes: a. signals on s x , dx, a x , or en exceeding v+ or v- will be cl amped by internal diodes. limit forward di ode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 7.6 mw/c above 75 c. d. derate 12 mw/c above 75 c. e. derate 10 mw/c above 75 c. truth table dg408l a 2 a 1 a 0 en on switch xxx0 none 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 truth table dg409l a 1 a 0 en on switch x x 0 none 001 1 011 2 101 3 111 4 ordering information dg408l temp. range package part number - 40 c to 85 c 16-pin soic dg408ldy dg408ldy-e3 dg408ldy-t1 dg408ldy-t1-e3 16-pin tssop dg408ldq dg408ldq-e3 dg408ldq-t1 dg408ldq-t1-e3 ordering information dg409l temp. range package part number - 40 c to 85 c 16-pin soic dg409ldy dg409ldy-e3 dg409ldy-t1 dg409ldy-t1-e3 16-pin tssop dg409ldq DG409LDQ-E3 dg409ldq-t1 dg409ldq-t1-e3 absolute maximum ratings parameter limit unit voltage referenced v+ to v- 14 v gnd 7 digital inputs a , v s , v d (v-) - 0.3 to (v) + 0.3 current (any terminal) 30 ma peak current, s or d (pulsed at 1 ms, 10 % duty cycle max.) 100 storage temperature (a suffix) - 65 to 150 c (d suffix) - 65 to 125 power dissipation (package) b 16-pin plastic tssop c 650 mw 16-pin narrow soic c 600 16-pin cerdip d 900 lcc-20 e 750
document number: 71342 s11-1066-rev. g, 30-may-11 www.vishay.com 3 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. leakage parameters are guaranteed by worst case te st condition and not subject to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, no t subject to production test. f. v in = input voltage to perform proper function. g. ? r ds(on) = r ds(on) max - r ds(on) min. h. worst case isolation occurs on channel 4 do to proximity to the drain pin. i. r ds(on) flatness is measured as the difference between the minimum and maximum measured values across a defined analog signal. specifications (single supply 12 v) parameter symbol test conditions unless otherwise specified v+ = 12 v, 10 % , v- = 0 v v en = 0.8 v or 2.4 v f temp. b typ. d a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. c max. c min. c max. c analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) v d = 10.8 v, v d = 2 v or 9 v, i s = 10 ma sequence each switch on room full 17 29 38 29 35 ? r ds(on) matching between channels g ? r ds v d = 10.8 v, v d = 2 v or 9 v i s = 10 ma room 1 3 3 on-resistance flatness i r flat(on) room 3 7 7 switch off leakage current i s(off) v en = 0 v, v d = 11 v or 1 v v s = 1 v or 11 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i d(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current i d(on) v s = v d = 1 v or 11 v room full - 1 - 15 1 15 - 1 - 10 1 10 digital control logic high input voltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.8 0.8 input current i in v ax = v en = 2.4 v or 0.8 v full - 1.5 1.5 - 1 1 a dynamic characteristics transition time t trans v s1 = 8 v, v s8 = 0 v, (dg408l) v s1b = 8 v, v s4b = 0 v, (dg409l) see figure 2 room full 30 60 68 60 65 ns break-before-make time t open v s(all) = v da = 5 v see figure 4 room full 11 1 1 enable turn-on time t on(en) v ax = 0 v, v s1 = 5 v (dg408l) v ax = 0 v, v s1b = 5 v (dg409l) see figure 3 room full 38 55 60 55 60 enable turn-off time t off(en) room full 18 25 35 25 30 charge injection e q c l = 1 nf, v gen = 0 v, r gen = 0 ? room 1 5 5 pc off isolation e, h oirr f = 100 khz, r l = 1 k ? room - 70 db crosstalk e x ta l k room - 82 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 7 pf drain off capacitance e c d(off) f = 1 mhz, v d = 2.4 v, v en = 0 v room 20 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v (dg409l only) room 31 power supplies power supply range v+ 3 12 3 12 v power supply current i+ v en = v a = 0 v or 5 v room 0.2 0.7 0.7 ma
www.vishay.com 4 document number: 71342 s11-1066-rev. g, 30-may-11 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. leakage parameters are guaranteed by worst case test condition and not subject to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this datas heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occurs on cha nnel 4 do to proximity to the drain pin. i. r ds(on) flatness is measured as the difference between the minimu m and maximum measured values across a defined analog signal. specifications (dual supply v+ = 5 v, v - = - 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, 10 % , v- = - 5 v v en = 0.6 v or 2.4 v f temp. b typ. d a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. c max. c min. c max. c analog switch analog signal range e v analog full - 5 5 - 5 5 v drain-source on-resistance r ds(on) v d = 3.5 v, i s = 10 ma sequence each switch on room full 20 40 50 40 50 ? switch off leakage current a i s(off) v+ = 5.5 , v- = 5.5 v v en = 0 v, v d = 4.5 v, v s = 4.5 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i d(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current a i d(on) v+ = 5.5 v, v- = - 5.5 v v en = 2.4 v, v d = 4.5 v, v s = 4.5 v room full - 1 - 15 1 15 - 1 - 10 1 10 digital control logic high input voltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.6 0.6 input current a i in v ax = v en = 2.4 v or 0.6 v full - 1.5 1.5 - 1 1 a dynamic characteristics transition time e t trans v s1 = 3.5 v, v s8 = - 3.5 v, (dg408l) v s1b = 3.5 v, v s4b = - 3.5 v, (dg409l) see figure 2 room full 30 60 78 60 65 ns break-before-make time e t open v s(all) = v da = 3.5 v see figure 4 room full 81 1 enable turn-on time e t on(en) v ax = 0 v, v s1 = 3.5 v (dg408l) v ax = 0 v, v s1b = 3.5 v (dg409l) see figure 3 room full 25 55 68 55 60 enable turn-off time e t off(en) room full 20 40 50 40 45 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 6 pf drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 15 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v room 29
document number: 71342 s11-1066-rev. g, 30-may-11 www.vishay.com 5 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. leakage parameters are guaranteed by worst case te st condition and not subject to production test. b. room = 25 c, full = as determi ned by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datas heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, no t subject to production test. f. v in = input voltage to perform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occurs on channel 4 do to proximity to the drain pin. i. r ds(on) flatness is measured as the differenc e between the minimum and maximum measur ed values across a defined analog signal. specifications (single supply 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, 10 % , v- = 0 v v en = 0.6 v or 2.4 v f temp. b typ. d a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. c max. c min. c max. c analog switch analog signal range e v analog full 0 5 0 5 v drain-source on-resistance r ds(on) v+ = 4.5 v, v d or v s = 1 v or 3.5 v, i d = 5 ma room full 35 49 62 40 62 ? r ds(on) matching between channels g ? r ds v+ = 4.5 v, v d = 1 v or 3.5 v, i s = 5 ma room 1.5 3 3 on-resistance flatness i r flat(on) room 4 4 switch off leakage current a i s(off) v+ = 5.5 v, v s = 1 v or 4 v v d = 4 v or 1 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i d(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current a i d(on) v+ = 5.5 v, v d = v s = 1 v or 4 v sequence each switch on room full - 1 - 15 1 15 - 1 - 10 1 10 digital control logic high input voltage v inh v+ = 5 v full 2.4 2.4 v logic low input voltage v inl full 0.6 0.6 input current a i in v ax = v en = 2.4 v or 0.6 v full - 1.5 1.5 - 1 1 a dynamic characteristics transition time e t trans v s1 = 3.5 v, v s8 = 0 v, (dg408l) v s1b = 3.5 v, v s4b = 0 v, (dg409l) see figure 2 room full 44 125 138 125 135 ns break-before-make time e t open v s(all) = v da = 3.5 v, see figure 4 room full 17 1 1 enable turn-on time e t on(en) v ax = 0 v, v s1 = 3.5 v (dg408l) v ax = 0 v, v s1b = 3.5 v (dg409l) see figure 3 room full 43 60 70 60 65 enable turn-off time e t off(en) room full 26 45 60 45 50 charge injection e q c l = 1 nf, r gen = 0 ? , v gen = 0 ? room 1 5 5 pc off isolation e, h oirr f = 100 khz, r l = 1 k ? room - 70 db crosstalk e x ta l k room - 80 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 8 pf drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 21 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v (dg409l only) room 32
www.vishay.com 6 document number: 71342 s11-1066-rev. g, 30-may-11 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. leakage parameters are guaranteed by worst case test condition and not subject to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this datas heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occurs on cha nnel 4 do to proximity to the drain pin. i. r ds(on) flatness is measured as the difference between the minimu m and maximum measured values across a defined analog signal. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (single supply 3 v) parameter symbol test conditions unless otherwise specified v+ = 3 v, 10 % , v- = 0 v v en = 0.4 v or 2 v f temp. b typ. d a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. c max. c min. c max. c analog switch analog signal range e v analog full 0 3 0 3 v drain-source on-resistance r ds(on) v+ = 2.7 v, v d = 0.5 or 2.2 v, i s = 5 ma room full 60 80 105 80 100 ? switch off leakage current a i s(off) v+ = 3.3 v, v s = 2 or 1 v, v d = 1 or 2 v room full - 1 - 15 1 15 - 1 - 10 1 10 na i d(off) room full - 1 - 15 1 15 - 1 - 10 1 10 channel on leakage current a i d(on) v+ = 3.3 v, v d = v s = 1 or 2 v sequence each switch on room full - 1 - 15 1 15 - 1 - 10 1 10 digital control logic high input voltage v inh full 2 2 v logic low input voltage v inl full 0.4 0.4 input current a i in v ax = v en = 2.4 v or 0.4 v full - 1.5 1.5 - 1 1 a dynamic characteristics transition time t trans v s1 = 1.5 v, v s8 = 0 v, (dg408l) v s1b = 1.5 v, v s4b = 0 v, (dg409l) see figure 2 room full 75 150 175 150 175 ns break-before-make time t open v s(all) = v da = 1.5 v, see figure 4 room full 32 1 1 enable turn-on time t on(en) v ax = 0 v, v s1 = 1.5 v (dg408l) v ax = 0 v, v s1b = 1.5 v (dg409l) see figure 3 room full 70 95 115 95 105 enable turn-off time t off(en) room full 55 100 115 100 105 charge injection e q c l = 1 nf, r gen = 0 ? , v gen = 0 v room 0.4 5 5 pc off isolation e, h oirr r l = 1 k ? , f = 100 khz room - 70 db crosstalk e x ta l k room - 79 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 8 pf drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 19 drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2 v (dg409l only) room 33
document number: 71342 s11-1066-rev. g, 30-may-11 www.vishay.com 7 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) r ds(on) vs. v d and power supply input threshold vs. v+ supply voltage r ds(on) vs. v d and temperature 0 10 20 30 40 50 60 70 80 024681012 v d - drain voltage (v) v+ = 2.7 v r ds(on) - drain-source on-resistance ( ? ) v+ = 4.5 v v+ = 12 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2 4 6 8 10 12 14 v+ - positive supply voltage (v) v t (v) upper threshold limit low threshold limit 0 5 10 15 20 25 30 35 - 6 - 4 - 2 0 2 4 6 25 ? c r ds(on) - drain-source on-resistance ( ? ) v d - drain v oltage (v) - 55 c 125 ? c 85 ? c r ds(on) vs. v d and power supply r ds(on) vs. v d and temperature switching time vs. positive supply voltage 0 5 10 15 20 25 - 5 - 3 - 1 1 3 5 r ds(on) - drain-source on-resistance ( ? ) v d - drain voltage (v) v+ = 5 v v- = - 5 v 0 10 20 30 40 50 0123456 25 ? c r ds(on) - drain-source on-resistance ( ? ) v d - drain voltage (v) - 55 c 85 ? c 125 ? c 0 10 20 30 40 50 60 70 02468101214 v+ - positive supply voltage (v) switching speed (ns) t on t trans t off
www.vishay.com 8 document number: 71342 s11-1066-rev. g, 30-may-11 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) leakage current vs. analog voltage charge injection vs. analog voltage drain/source capacitance vs. analog voltage - 40 - 30 - 20 - 10 0 10 - 5 - 3 - 1 1 3 5 v d , v s - analog voltage (v) leakage current (pa) i s(off) i d(on) i d(off) 0.0 0.2 0.4 0.6 0.8 1.0 - 5 0 5 10 q - charge injection (pc) v s - source voltage (v) v+ = 5 v v- = - 5 v v+ = 5 v v- = 0 v v+ = 12 v v- = 0 v c l = 1000 pf 0 5 10 15 20 25 30 35 24681012 c s(off) c d , c s - drain/source capacitance (pf) v+ = 12 v v- = 0 v c d(off) c d(on) 0 switching time vs. dual power supply voltage insertion loss, off isolation and crosstalk vs. frequency (single supply) drain/source capacitance vs. analog voltage 0 5 10 15 20 25 30 35 40 3456 - dual power supply voltage (v) switching speed (ns) t trans t on t off 0.1 - 110 1 - 30 10 - 70 - 50 100 1000 - 90 loss (db) v+ = 3 v v- = 0 v r l = 50 ? off isolation crosstalk insertion loss - 3 db = 280 mhz 10 - 10 frequency (mhz) c d , c s - drain/source capacitance (pf) 0 5 10 15 20 25 30 35 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 v+ = 5 v v- = - 5 v c s(off) c d(off) c d(on)
document number: 71342 s11-1066-rev. g, 30-may-11 www.vishay.com 9 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 schematic diagram (typical channel) test circuits figure 1. en a 0 s 1 d v+ s n v- decode/ drive level shift v- v+ a x gnd v+ figure 2. transition time a 1 a 0 a 2 a 1 a 0 v+ v- en v+ v- gnd d 35 pf v o s 1 s 2 - s 7 s 8 50 ? 300 ? v s8 v s1 v+ v- en v+ v- gnd 35 pf v o s 1b s 1a - s 4a , d a s 4b 300 ? d b logic input switch output v s8 v o t trans t r < 20 ns t f < 20 ns s 8 on (dg408l) or s 4 on (dg409l) s 1 on t trans 50 % v s1 50 % 90 % 90 % 3 v 0 v dg408l dg409l v sb4 v s1 3 v 3 v v ax 50 ?
www.vishay.com 10 document number: 71342 s11-1066-rev. g, 30-may-11 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 3. enable switching time logic input switch output v o t r < 20 ns t f < 20 ns 3 v 0 v 0 v t off(en) t on(en) 50 % 90 % 10 % v o en s 1 s 2 - s 8 a 0 a 1 a 2 50 ? 300 ? v o v+ gnd v- d 35 pf v- v+ s 1b s 1a - s 4a , d a s 2b - s 4b d b en a 0 a 1 50 ? 300 ? v o v+ gnd v- 35 pf v- dg408l dg409l v s1 v+ v s1 figure 4. break-before-make interval 50 % 80 % logic input switch output v o v s t open t r < 20 ns t f < 20 ns 0 v 3 v 0 v en v+ gnd v- 35 pf v- 3 v a 2 d b , d all s and d a 300 ? v o 50 ? bbm.5 4/9 a 1 a 0 dg408l dg409l v s1
document number: 71342 s11-1066-rev. g, 30-may-11 www.vishay.com 11 vishay siliconix dg408l, dg409l this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71342 . figure 5. charge injection a 0 en a 1 a 2 v o v+ gnd v- d v g r g s x c l 1 nf channel select 3 v 0 v off on logic input switch output ? v o ? v o is the measured voltage due to charge transfer error q, when the channel turns off. q = c l x ? v o off v+ v- figure 6. off isolation figure 8. insertion loss r l 1 k ? v o v+ gnd v- a 2 d a 1 a 0 s 8 s x v s en r g = 50 ? off isolation = 20 log v out v in v in v+ v- r l 1 k ? a 2 v o d r g = 50 ? insertion loss = 20 log v out a 1 v in a 0 v s s 1 v+ gnd v- en v- v+ figure 7. crosstalk figure 9. source drain capacitance r l 1 k ? v o v+ gnd v- a 2 d a 1 a 0 s 8 s x v s en r g = 50 ? crosstalk = 20 log v out v in v in s 1 v+ v- f = 1 mhz s 1 d en gnd v+ v- meter hp4192a impedance analyzer or equivalent s 8 a 1 a 2 a 0 channel select v- v+
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
vishay siliconix package information document number: 74417 23-oct-06 www.vishay.com 1 symbols dimensions in millimeters min nom max a - 1.10 1.20 a1 0.05 0.10 0.15 a2 - 1.00 1.05 b 0.22 0.28 0.38 c - 0.127 - d 4.90 5.00 5.10 e 6.10 6.40 6.70 e1 4.30 4.40 4.50 e-0.65- l 0.50 0.60 0.70 l1 0.90 1.00 1.10 y--0.10 1036 ecn: s-61920-rev. d, 23-oct-06 dwg: 5624 tssop: 16-lead
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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